Widespread use of mobile or low power electronics has created a need for high performance integrated circuits capable of operation at subvolt (<1 volt) levels. Many attempts have been made to develop new transistor architectures with high performance, low operating voltage, and low leakage. For example, there has been significant research regarding the use of silicon on insulator (SOI) and three dimensional fin (multigate) transistors. However, such integrated circuit designs are typically incompatible with much of the existing fabrication and design infrastructure.
Further exacerbating the problems regarding the fabrication of subvolt transistor devices is that many integrated circuit designs now call for a variety of devices to be formed therein. For example, it is not uncommon for a circuit design to include subvolt transistor devices to be concurrently formed with other devices on a same integrated circuit die, such as high power transistors and analog devices. In addition to these different devices having different requirements for performance, these devices are also typically associated with different fabrication conditions to achieve this performance. In some instances, these different fabrication conditions can conflict with each other. Accordingly, in order to ensure sufficient yield of operable devices in such cases, a compromise between the fabrication and performance of the subvolt devices and the other devices is typically required. For example, in many designs, the performance requirements are relaxed in order to allow selection of conditions that allow for the fabrication of the subvolt devices and other devices on a same substrate, conditions that are often suboptimal. As a result, even though there may be a high yield of operable devices, the performance of the subvolt device, the other devices, or both, may be degraded in such integrated circuit die.